Fast Recovery Diodes（FRD）快恢复二极管

快恢复二极管（Fast Recovery Diodes，简称FRD）是一种具有开关特性好、反向恢复时间短特点的半导体二极管，主要应用于开关电源、PWM脉宽调制器、变频器等电子电路中，作为高频整流二极管、续流二极管或阻尼二极管使用。 快恢复二极管的内部结构与普通PN结二极管不同，它属于PIN结型二极管，即在P型硅材料与N型硅材料中间增加了基区I，构成PIN硅片。因基区很薄，反向恢复电荷很小，所以快恢复二极管的反向恢复时间较短，正向压降较低，反向击穿电压（耐压值）较高。

Fast Recovery Diodes (FRD), often referred to as fast recovery diodes, are semiconductor diodes known for their excellent switching characteristics and short reverse recovery time. They are primarily used in electronic circuits such as power supplies, PWM (Pulse Width Modulation) controllers, inverters, serving as high-frequency rectifier diodes, freewheeling diodes, or snubber diodes.

The internal structure of a Fast Recovery Diode differs from a standard PN junction diode. It belongs to the PIN junction diode category, where an intrinsic (I) region is added between the P-type silicon material and N-type silicon material, forming a PIN silicon wafer. Because the intrinsic region is very thin, the reverse recovery charge is minimal, leading to a short reverse recovery time, low forward voltage drop, and high reverse breakdown voltage (voltage rating).

快恢复二极管结构
为了获得较快的反向恢复特性，通过改进阳极结构来控制其注入效率，以降低导通期间的少子注入。图1所示的快恢复二极管采用了不同阳极剖面结构。

To achieve faster reverse recovery characteristics, the injection efficiency is controlled by improving the anode structure to reduce minority carrier injection during conduction. The fast recovery diode shown in Figure 1 employs a different anode profile structure.

(1) 弱阳极二极管结构如图1a所示，它是通过降低普通pin二极管的阳极掺杂浓度形成的。其n+衬底与n外延层与普通pin二极管相同，只是p阳极区的掺杂浓度比普通pin二极管的p+阳极区掺杂浓度更低。采用此结构可降低阳极注入效率，提高反向恢复速度，并降低开关损耗。故这种结构也称为低损耗二极管(Low Loss Diode, LLD)。

Weak Anode Diode Structure, as shown in Figure 1a, is formed by reducing the anode doping concentration of a standard PIN diode. Its n+ substrate and n epitaxial layer are the same as a standard PIN diode, except that the doping concentration in the p anode region is lower than that in the p+ anode region of a standard PIN diode. This structure reduces anode injection efficiency, enhances reverse recovery speed, and reduces switching losses. Hence, this structure is also known as a Low Loss Diode (LLD).

  (2)发射极注入效率自调整二极管(SPEED)结构如图1b所示，它是在低掺杂的p阳极区中嵌入了高掺杂浓度的p+区。低电流密度下，pn结的注入效率较低，所以二极管的压降由正向压降较低的pnn+部分决定；高电流密度下，p+pn结的注入效率较高，所以二极管的压降由正向压降较低的p+pnn+部分决定。与普通pin二极管相比，SPEED结构在高电流密度下正向压降增加更少，有助于提高器件抗浪涌电流的能力，并提高反向恢复速度。

The structure of the Self-Adjusting Emitter Diode (SPEED), as shown in Figure 1b, involves embedding a highly doped p+ region into a lowly doped p anode region. At low current densities, the injection efficiency of the pn junction is low, so the diode's voltage drop is primarily determined by the low forward voltage drop of the pnn+ region. At high current densities, the injection efficiency of the p+pn junction is higher, causing the voltage drop to be determined by the low forward voltage drop of the p+pnn+ region. Compared to a standard PIN diode, the SPEED structure exhibits a smaller increase in forward voltage drop at high current densities, contributing to improved surge current capability and enhanced reverse recovery speed

  (3)静电屏蔽二极管(Static Shielding Diode,SSD)结构如图1c所示，它的阳极是由一个高掺杂的p+区环绕浅轻掺杂p区构成。由于轻掺杂p区有较低的注入效率，导致存储电荷减小。该结构可以改善反向恢复特性，但击穿电压较低。

The structure of the Static Shielding Diode (SSD), as shown in Figure 1c, features an anode surrounded by a highly doped p+ region, enclosing a lightly doped p region. The lightly doped p region has a lower injection efficiency, resulting in reduced stored charge. This structure can improve reverse recovery characteristics but comes at the cost of a lower breakdown voltage.

  (4)发射极短路型二极管(Emiller Short Type Diode,ESD)结构如图1d所示，它是在阳极区增加了部分n+控制区，以降低阳极的注入效率。同时在阳极侧也产生了一个寄生的n+pn-n晶体管。通过适当降低p阳极区的掺杂剂量，并控制n+区的尺寸，可以减小n+区下方p阳极区的横向电阻，从而避免寄生晶体管在反向恢复期间导通，并获得高击穿电压和低阳极注入效率。通常将p+与n+区做成精细的接触结构(如宽度Ln+=1µm,Lp=3µm，结深均为1µm，掺杂浓度为1x1019cm-3)，可以保证反向恢复期间n+p结的正偏压低于0.5V而不发生注入。东芝(Toshiba)公司采用该ESD结构巳研制出4kV耐压的二极管，在20℃下漏电流低于10µA，在125℃下漏电流在1mA左右，在100A/cm2的正向电流密度下正向压降为1.24V,且反向恢复峰值电流、恢复时间及反向恢复电荷明显减小。

The structure of the Emiller Short Type Diode (ESD), as shown in Figure 1d, involves adding a partial n+ control region to the anode region to reduce anode injection efficiency. Simultaneously, a parasitic n+pn-n transistor is formed on the anode side. By appropriately reducing the doping level of the p anode region and controlling the size of the n+ region, the lateral resistance below the p anode region is reduced. This prevents the parasitic transistor from conducting during reverse recovery and results in a high breakdown voltage and low anode injection efficiency.

Typically, a fine contact structure is used for the p+ and n+ regions (e.g., with a width of Ln+=1µm, Lp=3µm, a junction depth of 1µm, and a doping concentration of 1x1019cm-3). This structure ensures that the forward bias voltage across the n+p junction remains below 0.5V during reverse recovery, preventing injection. Toshiba has used this ESD structure to develop diodes with a 4kV breakdown voltage. These diodes exhibit leakage currents below 10µA at 20℃, around 1mA at 125℃, and a forward voltage drop of 1.24V at a forward current density of 100A/cm2. Additionally, they show a significant reduction in reverse recovery peak current, recovery time, and reverse recovery charge.

  (5)注入效率逆增长(IDEE)二极管结构如图1e所示，它是通过离子注入和高温推进将阳极区做成了分离的高掺杂深p+区，且深p+区之间的n-区形成沟道，使阳极注入效率与常规的pn结的注入效率变化趋势相反，即随阳极电流的上升而逐渐增大，有利于降低大电流下的通态功耗，提高二极管抗浪涌电流的能力。同时由于阳极p+区间距很小，截止状态下沟道区会被p+n结的电场屏蔽，所以对击穿电压几乎没有影响。

The Injected Efficiency Inverse Increasing (IDEE) Diode structure, as shown in Figure 1e, is achieved by ion implantation and high-temperature annealing to create separated, highly doped deep p+ regions in the anode region. The n- region formed between these deep p+ regions creates a channel, causing the anode injection efficiency to exhibit an opposite trend to the conventional pn junction. In this case, the anode injection efficiency gradually increases with anode current, which is advantageous for reducing on-state power dissipation at high currents and enhancing the diode's surge current capability. Furthermore, due to the close proximity of the anode p+ regions, the channel region is shielded from the electric field of the p+n junction in the off state, resulting in minimal impact on the breakdown voltage.